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TECHNICAL DATA
IW4001B
Quad 2-Input NOR Gate
High-Voltage Silicon-Gate CMOS
The IW4001B NOR gates provide the system designer with direct emplementation of the NOR function. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
ORDERING INFORMATION IW4001BN Plastic IW4001BD SOIC TA = -55 to 125 C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
FUNCTION TABLE
Inputs PIN 14 =VCC PIN 7 = GND A L L H H B L H L H Output Y H L L L
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IW4001B
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN PD PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260
Unit V V V mA mW mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IW4001B
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions VOUT=0.5V VOUT=1.0 V VOUT=1.5V V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.25 0.5 1.0 5.0 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.25 0.5 1.0 5.0 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 7.5 15 30 150 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V
VIL
Maximum Low -Level VOUT=0.5 V or VCC - 0.5 V Input Voltage VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=GND
V
VOH
V
VOL
VIN=GND or VCC
V
IIN ICC
VIN= GND or VCC VIN= GND or VCC
A A
IOL
Minimum Output Low VIN= GND or VCC (Sink) Current UOL=0.4 V UOL=0.5 V UOL=1.5 V Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V
mA
IOH
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IW4001B
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input tr=tf=20 ns)
VCC Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance V 5.0 10 15 5.0 10 15 250 120 90 200 100 80 Guaranteed Limit -55C 25C 250 120 90 200 100 80 7.5 125C 500 240 180 400 200 160 Unit ns
tTLH, tTHL
ns
CIN
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM (1/4 of the Device)
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